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| M29W512B 512 Kbit (64Kb x8, Bulk) Low Voltage Single Supply Flash Memory s SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 55ns PROGRAMMING TIME - 10s per Byte typical PROGRAM/ERASE CONTROLLER - Embedded Byte Program algorithm - Embedded Chip Erase algorithm - Status Register Polling and Toggle Bits TSOP32 (NZ) 8 x 14mm PLCC32 (K) s s s s UNLOCK BYPASS PROGRAM COMMAND - Faster Production/Batch Programming LOW POWER CONSUMPTION - Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES 20 YEARS DATA RETENTION - Defectivity below 1 ppm/year ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 27h VCC s s s Figure 1. Logic Diagram s 16 A0-A15 W E G M29W512B 8 DQ0-DQ7 VSS AI02743 March 2000 1/18 M29W512B Figure 2. TSOP Connections Figure 3. PLCC Connections A11 A9 A8 A13 A14 NC W VCC NC NC A15 A12 A7 A6 A5 A4 A12 A15 NC NC VCC W NC 1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A14 A13 A8 A9 A11 G A10 E DQ7 9 M29W512B 25 17 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 AI02755 1 32 8 9 M29W512B 25 24 16 17 AI02976 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 Table 1. Signal Names A0-A15 DQ0-DQ7 E G W VCC VSS NC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground Not Connected Internally SUMMARY DESCRIPTION The M29W512B is a 512 Kbit (64Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP32 (8 x 14mm) and PLCC32 packages and it is supplied with all the bits erased (set to '1'). 2/18 M29W512B Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VCC VID Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Identification Voltage Value 0 to 70 -50 to 125 -65 to 150 -0.6 to 4 -0.6 to 4 -0.6 to 13.5 Unit C C C V V V Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions. SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A15). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power-up, power-down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1F capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. Vss Ground. The VSS Ground is the reference for all voltage measurements. 3/18 M29W512B BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 3, Bus Operations, for a summary. Typically glitches of less than 5ns are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8, Read Mode AC Waveforms, and Table 10, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 9 and 10, Write AC Waveforms, and Tables 11 and 12, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V IH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC 0.2V. For the Standby current level see Table 9, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 3, Bus Operations. Table 3. Bus Operations Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code Note: X = VIL or VIH. E VIL VIL X VIH VIL VIL G VIL VIH VIH X VIL VIL W VIH VIL VIH X VIH VIH Address Inputs Cell Address Command Address X X A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Data Inputs/Outputs Data Output Data Input Hi-Z Hi-Z 20h 27h 4/18 M29W512B COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The commands are summarized in Table 4, Commands. Refer to Table 4 in conjunction with the text descriptions below. Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Chip Erase operation the memory will take about 10s to abort the Chip Erase. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Chip Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select command is used to read the Manufacturer Code and the Device Code. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either V IL or VIH. The Manufacturer Code for STMicroelectronics is 20h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either V IL or VIH. The Device Code for the M29W512B is 27h. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. Table 4. Commands Command Length Bus Write Operations 1st Addr X 555 555 555 555 X X 555 Data F0 AA AA AA AA A0 90 AA 2AA 2AA 2AA 2AA PA X 2AA 55 55 55 55 PD 00 55 555 80 555 AA 2AA 55 555 10 X 555 555 555 F0 90 A0 20 PA PD 2nd Addr Data 3rd Addr Data 4th Addr Data 5th Addr Data 6th Addr Data 1 Read/Reset 3 Auto Select Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase 3 4 3 2 2 6 Note: X Don't Care, PA Program Address, PD Program Data. All values in the table are in hexadecimal. The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don't Care. Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID or Device ID. Program, Unlock Bypass Program, Chip Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued. 5/18 M29W512B During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 5. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. The Chip Erase command must be used to set all the bits in the memory from '0' to '1'. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. The operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/ Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Chip Erase Command. The Chip Erase command can be used to erase the memory. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. Typical chip erase times are given in Table 5. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase command sets all of the bits in the memory to '1'. All previous data is lost. Table 5. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70C) Parameter Chip Erase (All bits in the memory set to `0') Chip Erase Program Chip Program Program/Erase Cycles Note: 1. TA = 25C, VCC = 3.3V. Min Typ (1) 0.5 1 10 0.7 Typical after 100k W/E Cycles (1) 0.5 1 10 0.7 Max Unit sec 6 200 4 sec s sec cycles 100,000 6/18 M29W512B STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 6, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. Figure 4, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or any address while erasing the chip. Table 6. Status Register Bits Operation Program Program Error Chip Erase Erase Error Note: Unspecified data bits should be ignored. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. Figure 5, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set at '0' back to '1' and attempting to do so may or may not set DQ5 at '1'. In both cases, a successive Bus Read operation will show the bit is still '0'. The Chip Erase command must be used to set all the bits the memory from '0' to '1'. Address Any Address Any Address Any Address Any Address DQ7 DQ7 DQ7 0 0 DQ6 Toggle Toggle Toggle Toggle DQ5 0 1 0 1 7/18 M29W512B Figure 4. Data Polling Flowchart START START Figure 5. Data Toggle Flowchart READ DQ5 & DQ7 at VALID ADDRESS READ DQ5 & DQ6 READ DQ6 DQ7 = DATA NO NO YES DQ6 = TOGGLE YES NO DQ5 =1 YES NO DQ5 =1 YES READ DQ6 TWICE READ DQ7 at VALID ADDRESS DQ7 = DATA NO FAIL YES DQ6 = TOGGLE YES NO PASS FAIL PASS AI01370B AI03598 8/18 M29W512B Table 7. AC Measurement Conditions M29W512B Parameter 55 VCC Supply Voltage Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 3.0 to 3.6V 30pF 10ns 0 to 3V 1.5V 70 / 90 / 120 2.7 to 3.6V 30pF 10ns 0 to 3V 1.5V Figure 6. AC Testing Input Output Waveform Figure 7. AC Testing Load Circuit 0.8V 3V 1.5V 0V AI01417 1N914 3.3k DEVICE UNDER TEST CL = 30pF OUT CL includes JIG capacitance AI02978 Table 8. Capacitance (TA = 25 C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: Sampled only, not 100% tested. 9/18 M29W512B Table 9. DC Characteristics (TA = 0 to 70C) Symbol ILI ILO ICC1 ICC2 ICC3 (1) VIL VIH VOL VOH VID IID VLKO (1) Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Supply Current (Program/Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Identification Voltage Identification Current Program/Erase Lockout Supply Voltage A9 = VID 1.8 IOL = 1.8mA IOH = -100A VCC - 0.4 11.5 12.5 100 2.3 Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIH, f = 6MHz E = VCC 0.2V Program/Erase Controller active -0.5 2 Min Max 1 1 10 100 20 0.8 VCC + 0.5 0.45 Unit A A mA A mA V V V V V A V Note: 1. Sampled only, not 100% tested. 10/18 M29W512B Table 10. Read AC Characteristics (TA = 0 to 70C) M29W512B Symbol Alt Parameter Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition Test Condition 55 tAVAV tAVQV tELQX (1) tELQV tGLQX (1) tGLQV tEHQZ (1) tGHQZ (1) tEHQX tGHQX tAXQX tRC tACC tLZ tCE tOLZ tOE tHZ tDF tOH E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Min Max Min Max Min Max Max Max Min 55 55 0 55 0 30 20 20 0 70 70 70 0 70 0 30 25 25 0 90 / 120 90 90 0 90 0 35 30 30 0 ns ns ns ns ns ns ns ns ns Unit Note: 1. Sampled only, not 100% tested. Figure 8. Read Mode AC Waveforms tAVAV A0-A15 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7 tGHQX tGHQZ VALID AI02977 VALID tAXQX tEHQX tEHQZ 11/18 M29W512B Table 11. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 C) M29W512B Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tVCHEL tOEH tVCS Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter 55 Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low Write Enable High to Output Enable Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Min 55 0 40 25 0 0 30 0 40 0 0 50 70 70 0 45 30 0 0 30 0 45 0 0 50 90 / 120 90 0 45 45 0 0 30 0 45 0 0 50 ns ns ns ns ns ns ns ns ns ns ns s Unit Figure 9. Write AC Waveforms, Write Enable Controlled tAVAV A0-A15 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ7 VALID tWHDX tWLWH tWHGL tWHEH VCC tVCHEL AI02757 12/18 M29W512B Table 12. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 C) M29W512B Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tVCHWL tOEH tVCS Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 55 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low Chip Enable High to Output Enable Low VCC High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Min 55 0 40 25 0 0 30 0 40 0 0 50 70 70 0 45 30 0 0 30 0 45 0 0 50 90 / 120 90 0 45 45 0 0 30 0 45 0 0 50 ns ns ns ns ns ns ns ns ns ns ns s Unit Figure 10. Write AC Waveforms, Chip Enable Controlled tAVAV A0-A15 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ7 VALID tEHDX tELEH tEHGL tEHWH VCC tVCHWL AI02758 13/18 M29W512B Table 13. Ordering Information Scheme Example: Device Type M29 Operating Voltage W = VCC = 2.7 to 3.6V Device Function 512B = 512 Kbit (64Kb x8), Bulk Speed 55 = 55 ns 70 = 70 ns 90 = 90 ns 120 = 120 ns Package NZ = TSOP32: 8 x 14 mm K = PLCC32 Temperature Range 1 = 0 to 70 C Option T = Tape & Reel Packing M29W512B 70 NZ 1 T Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 14/18 M29W512B Table 14. Revision History Date July 1999 First Issue Document type: from Preliminary Data to Data Sheet Status Register bit DQ5 clarification Data Polling Flowchart diagram change (Figure 4) Data Toggle Flowchart diagram change (Figure 5) Revision Details 03/09/00 15/18 M29W512B Table 15. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data mm Symbol Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 13.80 12.30 7.90 - 0.50 0 32 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 14.20 12.50 8.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.5433 0.4843 0.3110 - 0.0197 0 32 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.5591 0.4921 0.3189 - 0.0276 5 inches Figure 11. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline A2 1 N e E B N/2 D1 D A CP DIE C TSOP-a A1 L Drawing is not to scale. 16/18 M29W512B Table 16. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data Symbol A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 0.89 1.27 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 - 0.00 - 32 7 9 0.10 mm Typ Min 2.54 1.52 Max 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.25 - 0.0350 0.0500 0.0130 0.0260 0.4850 0.4469 0.3902 0.5850 0.5469 0.4902 - 0.0000 - 32 7 9 0.0039 Typ inches Min 0.1000 0.0598 Max 0.1402 0.0949 0.0150 0.0209 0.0319 0.4949 0.4551 0.4299 0.5949 0.5551 0.5299 - 0.0098 - Figure 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline D D1 1N A1 A2 B1 Ne E1 E F 0.51 (.020) D2/E2 B e 1.14 (.045) Nd A R CP PLCC Drawing is not to scale. 17/18 M29W512B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 18/18 |
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